(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating low and high voltage flash memory devices.
(2) Description of the Prior Art
Developments in the semiconductor industry have over the years focused on a wide array of technical disciplines, device designs and device packaging approaches. Improved semiconductor performance can be obtained following one or more of these avenues. Where a large number of semiconductor improvements have been obtained by device miniaturization, other approaches have sought to improve device performance by creating multifunction devices on one semiconductor die. Historically, semiconductor devices have been broadly divided in functions of data manipulation (logic devices) or data storage (memory devices). Devices that address these two different data processing functions have also historically been stored on different physical devices. Where however memory cells are created on a device that mostly functions as a data storage and data retrieval device, the actual memory cells within the device are typically surrounded by peripheral functions such as address decoders, read/write buffers and sense amplifiers.
The creation of many semiconductor devices starts with the growing of a layer of gate oxide over the surface where the device is to be located. The gate oxide is a thin thermal oxide, which allows better adhesion between the overlying layers (for instance nitride) and the (underlying) silicon and acts as a stress relaxation layer during field oxidation. Gate oxide can be formed by thermal oxidation of the underlying silicon and can also be formed in conjunction with a deposited oxide layer, nitride layer or any other material suitable for use as a gate dielectric. Gate oxide is usually formed as a silicon dioxide material but may be a composite oxide, such as TEOS and silicon dioxide, or a nitride oxide layer or a like gate dielectric. A gate oxide layer can for instance be grown in an oxidation steam ambient at a temperature between about 850 and 1000 degrees C. to a thickness between about 50 and 250 Angstrom.
Device performance is highly dependent on the thickness of the layer of gate oxide. In devices that combine FET devices with surrounding logic devices, the combined function that is provided by one semiconductor device requires the deposition of gate oxide layers of different thickness. Typically, surrounding logic functions required the use of a thin layer of gate oxide to enhance overall device performance while a thicker gate oxide is required in view of the required higher gate voltage for the FET access transistor of DRAM cells. As an example, with a voltage bias of about 2 volts of the substrate on which a FET memory device is created, a voltage difference of about 5 volts is required between the gate electrode and the substrate resulting in a gate voltage of 7 volts for the FET access transistor of the memory cells. The FET's of the logic portion of the circuit however require a gate voltage of about 3.3 volts, making it clear that layers of pad oxide are required for these devices that are of different thickness.
Another application where gate oxide layers of different thickness is required is in the application of MOS devices where combined PMOS and NMOS devices are created that form a converter. The majority carriers of PMOS devices are holes; the majority carriers of NMOS devices are electrons. Holes have a considerable lower mobility than electrons resulting in a lower drive capability of the PMOS device To compensate for this and to equalize the drive capability of the two types of devices, either the gate of the PMOS device is widened (allowing more drive current for a given gate voltage) or the thickness of the gate oxide layers for the two types of devices is adjusted allowing for higher gate current while maintaining gate width the same. Of these two solutions, the varying of the thickness of the gate oxide is the more promising since the widening of the gate electrode requires surface area, which is contrary to the desire of miniaturization of the devices. One of the techniques (provided by U.S. Pat. No. 5,330,920) that can be used to create gate oxide layers of different thickness is by selective ion implanting of a sacrificial layer of oxide that has been created over the surface of the substrate. The layer of gate oxide that is created over the surface that has been ion implanted is thinner that the gate oxide that is created over the surface that has not been subjected to ion implantation.
It is clear that the combination of providing different functions within the design of one semiconductor device brings with it the requirement for different thickness of the gate oxide layer. Typically, high voltage devices such as program and erase transistors require a relative thick layer of gate oxide that protects the device against high voltage breakdown. Where however device speed is important, a thin layer of oxide is required, operating speed is enhanced with a thin layer of oxide combined with a narrow gate structure (short channel length). These latter requirements gain further importance where devices with micron or sub-micron device features are implemented.
Layers of tunnel oxide are created under the floating gates of flash memory EEPROM devices. Data retention requirements of the EEPROM devices require that these layers of tunnel oxide have at least a minimum thickness, a requirement that may conflict with requirements of other oxide layer thickness of devices that are also contained within the EEPROM device. For non-volatile memory devices, this leads to the need for layers of oxide that have three different thicknesses. The data entry and erase transistors typically require (high date retention which means) relatively thick layers of pad oxide, the surrounding logic functions require (high operating speed which means) relatively thin layers of oxide and a thickness for the layer of tunnel oxide that is determined by requirements of device reliability.
Prior Art methods of forming oxide layers of different thickness use multiple steps of masking and oxide etch. The first layer created in this manner, typically the thickest layer, is initially grown on the surface of the substrate. This layer is masked with a layer of photoresist and etched thereby removing the unmasked layer of oxide from the substrate. The mask of photoresist is removed; a second layer of oxide is then grown over the surface of the substrate including the remaining first layer of oxide. This process results in a layer of oxide that has two thickness levels. This process can be repeated for the application where more than two levels of thickness are required, using a sequence of steps of deposition and etch. This process however suffers from the disadvantage of many sequential processing steps while the repeated use of photoresist, which is not easy to completely remove, results in layers of oxide of poor quality. Partial etch back of a deposited layer of oxide cab also be used but this method too suffers from the same disadvantages.
U.S. Pat. No. 5,672,521 (Barsan et al.) discloses I/I N2, an N-type ion I/I and uses a masking/oxide etch back to create 3 gate oxide thicknesses in different areas. This is very close to the invention.
U.S. Pat. No. 5,866,445 (Baumann) shows a N2 I/I to retard gate oxide thicknesses. See col.2, lines 57 to 67. Baumann does not show the invention's masking/oxide etch back step, but this may be considered obvious in combination with other patents. This is close to the invention.
U.S. Pat. No. 5,330,920 (Soleimani et al.) shows a dual gate oxide method using a N2 I/I.
U.S. Pat. No. 5,918,116 (Chittipedde) shows a process to form different gate oxide thicknesses by an amorphizing I/I.
U.S. Pat. No. 5,668,035 (Fang et al.) disclose dual gate oxide thickness by a masking/oxide step.